1. Field of the invention
The present invention relates to a device testing apparatus used for example in screening testing of semiconductor devices and the like.
This application is based on patent application No. Hei 9-253939 filed in Japan, the content of which is incorporated herein by reference.
2. Description of the Related Art
Heretofore, screening testing of semiconductor devices and the like is carried out using a device testing apparatus such as a burn-in apparatus, a test burn-in apparatus, a static burn-in apparatus, a dynamic burn-in apparatus, or a monitored burn-in apparatus.
Here the above-mentioned burn-in apparatus are for removing devices in which time and stress dependent faults occurs due to inherently defective semiconductor devices or to deviations in manufacture. The test burn-in apparatus is a burn-in apparatus having a function for judging if the semiconductor device is good or bad. The static burn-in apparatus is one which applies a rated voltage or a voltage exceeding this to the semiconductor device while under a high temperature, to thereby apply thermal and voltage stresses to the semiconductor device.
The dynamic burn-in apparatus is one which applies a rated voltage or a voltage exceeding this to the semiconductor device while at a constant temperature, and inputs to the input circuit of the semiconductor device a signal close to an actual operating signal. The monitored burn-in apparatus is a dynamic burn-in apparatus having a function for judging if the semiconductor device is good or bad, where not only is a signal input to the input circuit of the semiconductor device, but also the characteristics of the output circuit are monitored.
FIG. 4 is a partially cut away perspective diagram showing the construction of the main elements of the above-mentioned conventional device testing apparatus, and FIG. 5 is a side sectional view showing the construction of the main elements of the conventional device testing apparatus. Furthermore, FIG. 6 is an enlarged sectional view showing the construction inside the circle A of FIG. 5.
Numeral 1 in FIG. 4 denotes a DRV/CMP (driver/comparator) card having a plurality of signal lines for transmitting signals and the like, formed on a surface thereof. Numerals 2 denote a plurality of rectangular parallelepiped shaped male connectors respectively attached at predetermined spacing to one edge 1a of the DRV/CMP card 1. Here the male connector 2 is defined as a connector for which the molded shape is that of a male connector.
Numeral 3 denotes a motherboard disposed perpendicular to the DRV/CMP card 1. Numerals 4 denote a plurality of female connectors of C-shape in cross-section respectively provided corresponding to the male connectors 2, and respectively attached at a uniform spacing to one face 3a of the mother board 3. Here the female connector 4 is defined as a connector for which the molded shape is that of a female connector.
When the female connectors 4 are made up with three in a group, three groups are attached one above the other to the one face 3a of the mother board 3 as shown in FIG. 5. Furthermore as shown in FIG. 6, the female connectors 4 have a plurality of pins 5, and these pins 5 are respectively provided so as to pass through the motherboard 3. At the time of inserting the DRV/CMP card 1, the male connectors 2 fit into the female connectors 4.
Numerals 6 in FIG. 4 denote a plurality of edge connectors constituting female connectors provided respectively corresponding to the female connectors 4, and are respectively attached at uniform spacing to the other side 3b of the mother board 3. The edge connectors 6 are each formed with sockets (not shown in the figure).
When the edge connectors 6 are made up with three in a group, three groups are attached one above the other to the other face 3b of the mother board 3 as shown in FIG. 5, at positions one step lower than the female connectors 4. Furthermore as shown in FIG. 6, the edge connectors 6 have a plurality of pins 7, and these pins 7 are respectively provided so as to pass through the mother board 3, and so as to respectively connect electrically to the pins 5 via a plurality of signal lines (not shown in the figure) respectively formed on the other face 3b of the mother board 3.
Numeral 8 in FIG. 5 denotes a constant temperature oven provided close to the motherboard 3, for maintaining an interior space H thereof at a constant temperature. In FIG. 5 a part of the constant temperature oven 8 is shown, while in FIG. 4 the drawing for the constant temperature oven 8 is omitted.
Thin wide through holes 8c are respectively formed one above the other in the constant temperature oven 8, passing from the outer wall 8a to the inner wall 8b at locations respectively corresponding to the edge connectors 6.
Numerals 9 in FIG. 4 denote feed through boards provided corresponding respectively to the edge connectors 6, with one end 9a corresponding to the edge connectors 6 formed as a tongue. The one ends 9a of the feed through boards 9 are inserted into the edge connectors 6 shown in FIG. 6. The plate thickness of the feed through boards 9 is made slightly less than the vertical dimension (in FIG. 5) of the through holes 8c in FIG. 5.
The other ends of the feed through boards 9 shown in FIG. 4 are respectively fitted with edge connectors 10 having sockets (not shown in the figure). The edge connectors 10 are respectively connected electrically to the one ends 9a by signal lines formed on the respective surfaces of the feed through boards 9.
Numeral 11 denotes a test burn-in board which is slightly wider than the three feed through boards 9 arranged side by side, and which is disposed in the internal space H of the constant temperature oven 8 (refer to FIG. 5). At the time of testing, a plurality of devices 12 to be tested are mounted on the surface of the test burn-in board 11.
Tongues 11a are respectively formed on one end of the test burn-in board 11 at positions respectively corresponding to the edge connectors 10.
Next is a description of the operation of the above described conventional device testing apparatus. In FIG. 4, the male connectors 2 of the DRV/CMP card 1 are respectively fitted into the female connectors 4.
As a result, the DRV/CMP CARD 1 is supported relative to the mother board 3, and the signal lines formed on the surface of the DRV/CMP CARD 1 shown in FIG. 6, are electrically connected to the edge connector 6 via the male connectors 2, the female connectors 4, the pins 5, and the signal lines formed on the other face 3b of the mother board 3.
Furthermore, the other DRV/CMPs 1 shown in FIG. 5 are also respectively supported relative to the motherboard 3.
After this, the upper stage ones of feed through boards 9 shown in FIG. 5 are inserted in the direction of arrow Z1 in FIG. 5, into the through holes 8c from the inner wall 8b side of the constant temperature oven 8. Then the one ends 9a, (refer to FIG. 4) of the feed through boards 9 are inserted into the edge connectors 6.
As a result the feed through boards 9 are supported relative to the other face 3b of the mother board 3, and the edge connectors 10 are electrically connected to the signal lines shown in FIG. 6 formed on the surface of the DRV/CMP card 1, via the signal lines formed on the surface of the feed through boards 9, the edge connectors 6, the pins 7, the signal lines formed on the other face 3b of the mother board 3, the pins 5, the female connectors 4, and the male connectors 2.
The tongues 11a of the test burn-in board 11 shown in FIG. 4 are then respectively inserted into the edge connectors 10. As a result, the devices to be tested 12 are respectively connected electrically to the edge connectors 10 via signal lines formed on the surface of the test burn-in board 11.
In this connected condition, when a signal is supplied from a signal generator (not shown in the figure) to the signal lines formed on the surface of the DRV/CMP card 1, the signal is supplied to the devices to be tested 12 by way of a path Z2 shown in FIG. 6.
That is to say, the signal is supplied to the devices to be tested 12 via as shown in FIG. 6, the signal lines formed on the surface of the DRVICMP card 1, the male connectors 2, the female connectors 4, the pins 5, the signal line formed on the other face 3b of the mother board 3, the pins 7, the edge connectors 6, the signal lines formed on the surface of the feed through boards 9, the edge connectors 10 shown in FIG. 1, and the signal lines formed in the surface of the test burn-in board 11. In this way, testing is carried out with respect to the devices to be tested 12.
Incidentally, with the conventional device testing apparatus, from the point of testing efficiency, it is desirable to have as many as possible devices to be tested 12 mounted on the test burn-in board 11 within a range permitted by space.
However, with the conventional device testing apparatus, since the edge connectors 6 are used, only connections for a plurality of signal lines in a one dimensional array is possible. Hence there is inevitably a limit to the number of signals which can be supplied from the DRV/CMP card 1 via the feed through boards 9 to the test burn-in board 11.
Consequently, with the conventional device testing apparatus, since edge connectors 6 which can only connect to signal lines in a one dimensional array are used, then an increase in the number of signals which can be handled, and modification to the signal line array is not physically possible, and hence extendibility is limited.
Moreover, with the conventional device testing apparatus, there are cases where due to structural accuracy and the contact surface condition of the edge connectors 6 and the one ends 9a of the feed through boards 9, the reliability of the contact between the one ends 9a of the feed through boards 9 and the edge connectors 6 is low.
Furthermore, with the conventional device testing apparatus, since the path Z2 for the signal as shown in FIG. 6 is not straight, the signal transmission distance is increased.
As a result, with the conventional device testing apparatus, the delay time increases due to the delay occurring in the signal transmission, and the line capacity is increased, so that signal transmission characteristics are poor.
In addition, with the conventional device test apparatus, since a small gap occurs between the through holes 8c of the constant temperature oven 8 and the feed through boards 9, there is the problem that the air tightness and the insulation properties between the inner space H and the outer space cannot be maintained.